----------------------------------------------------------------------
-- Bit-serial 16-bit absolute value unit
-- Stephen West, James Carroll
-- BYU ECEn 620, October 2008
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	
entity BitSerialAbs16 is
	generic(
		word_length:integer:=8;
		code_vector_length:integer:=16;
		system_word_length:integer:=12
	);
	port(
		clk, lsb_in: in std_logic;
		bits_in: in std_logic_vector(code_vector_length-1 downto 0);
		abs_out: out std_logic_vector(code_vector_length-1 downto 0);
		lsb_out: out std_logic
	);
end entity;

architecture BitSerialAbs16 of BitSerialAbs16 is
    component BitSerialAbs is
		generic(
			word_length:integer:=8;
			code_vector_length:integer:=16;
			system_word_length:integer:=12
		);
		port(
			clk, bits_in, lsb_in:in std_logic;
				abs_out, lsb_out: out std_logic
		);
	end component;
	signal lsbs: std_logic_vector(code_vector_length-1 downto 0);
begin
	--single_abs:BitSerialAbs port map(clk=>clk, bits_in=>bits_in(0), abs_out=>abs_out(0), lsb_in=>'1', lsb_out=>lsbs(0));
	abs16x:for N in 0 to code_vector_length-1 generate
		single_abs:BitSerialAbs port map(clk=>clk, bits_in=>bits_in(N), abs_out=>abs_out(N), lsb_in=>lsb_in, lsb_out=>lsbs(N));
	end generate;
	lsb_out<=lsbs(0);
end architecture;
